TXSTSIE=Val_0x0, TSIE=Val_0x0, PMTIE=Val_0x0, PHYIE=Val_0x0, MDIOIE=Val_0x0, RXSTSIE=Val_0x0
Interrupt Enable Register
| PHYIE | PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of the ETH_MAC_INTERRUPT_STATUS[PHYIS] bit. 0 (Val_0x0): PHY interrupt is disabled 1 (Val_0x1): PHY interrupt is enabled |
| PMTIE | PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of the ETH_MAC_INTERRUPT_STATUS[PMTIS] bit. 0 (Val_0x0): PMT interrupt is disabled 1 (Val_0x1): PMT interrupt is enabled |
| TSIE | Timestamp Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of the ETH_MAC_INTERRUPT_STATUS[TSIS] bit. 0 (Val_0x0): Timestamp interrupt is disabled 1 (Val_0x1): Timestamp interrupt is enabled |
| TXSTSIE | Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of the ETH_MAC_INTERRUPT_STATUS[TXSTSIS] bit. 0 (Val_0x0): Timestamp status interrupt is disabled 1 (Val_0x1): Timestamp status interrupt is enabled |
| RXSTSIE | Receive Status Interrupt Enable When this bit is set, it enables the assertion of the interrupt signal because of the setting of the ETH_MAC_INTERRUPT_STATUS[RXSTSIS] bit. 0 (Val_0x0): Receive status interrupt is disabled 1 (Val_0x1): Receive status interrupt is enabled |
| MDIOIE | MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt when the ETH_MAC_INTERRUPT_STATUS[MDIOIS] bit is set. 0 (Val_0x0): MDIO interrupt is disabled 1 (Val_0x1): MDIO interrupt is enabled |